An Architectural and Circuit-Level Approach to Improving the Energy Efficiency of Microprocessor Memory Structures
نویسنده
چکیده
We present a combined architectural and circuit technique for reducing the energy dissipation of microprocessor memory structures. This approach exploits the subarray partitioning of high speed memories and varying application requirements to dynamically disable partitions during appropriate execution periods. When applied to 4-way set associative caches, trading off a 2% performance degradation yields a combined 40% reduction in L1 Dcache and L2 cache energy dissipation.
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تاریخ انتشار 1999